It is known to provide flash memory, such as NAND flash memory and NOR flash memory, to provide non-volatile data storage. The data storage capacity and access speeds of such flash memories have steadily increased with improvements in this technology. However, there are several sources of error inherent with such memories that can cause stored data to be lost or corrupted.
FIG. 1 of the accompanying drawings illustrates a NAND flash memory cell.
Charge is injected into a floating gate 2 under action of a control gate 4. Charge injected into the floating gate 2 remains held there as it is surrounded by oxide sidewalls 6, inter poly dielectric 8 and tunnel oxide 10. The floating gate 2 thus is held at a potential which varies in dependence upon the amount of charge injected into the floating gate 2. When the memory cell is read, the charge on the floating gate 2 influences the amount of current which flows between a source 12 and a drain 14 in a manner similar to that of a standard field effect transistor.
There are several error mechanisms which can occur and prevent the proper storage or reading of data to or from the cell of FIG. 1. These include cell charge loss, read disturb errors, program disturb errors and wear damage errors. Cell charge loss errors are caused by a change in the charge levels stored within the floating gate 2 due to charge leakage. These errors can be mitigated by refresh read-write cycles, such as those which are implicit in a wear levelling mechanism as will be familiar to those in this technical field. The read disturb and program disturb errors are connected to the configuration and operation of the NAND memory cell. The memories cells are not independent. The memory cells are typically arranged in a string on a bit line. A consequence of this is that access to a cell takes place through other cells. Furthermore, access for either read or write requires applying voltages which are typically significantly higher than the storage voltage levels in intervening cells. Read disturb errors are typically caused by charge migration due to application of the read voltage to the selected cell. Various forms of program disturb errors are caused by charge migration due to application of the program voltage to the selected cell. Finally, repeated application of the relatively high read and program voltages can result in the cell oxide layers becoming damaged such that the cell no longer retains charge as this leaks away.
Flash memory cells as originally produced provided two voltage levels storing one bit of data and corresponding to the floating gate being either charged or uncharged. Recent advances within the field have lead to the introduction of multilevel flash memory cells having more than two voltage levels, e.g. 2n voltage levels capable of storing a charge representing n-bits of data. This type of cell is termed a multilevel cell (MLC) and their introduction has resulted in an increase in storage density.
FIG. 2 of the accompanying drawings schematically illustrates the voltage levels which may be stored by an MLC having four voltage levels and thus capable of representing two bits of data. As illustrated, the different increasing voltage levels are used to represent a monotonically increasing two bit number. A storage or read error can occur when the voltage is sensed, with the result that the voltage level is incorrectly sensed as corresponding to one of the adjacent voltage levels. It is also possible that other errors may occur, such as the complete discharge of the MLC or other errors resulting in the read value being other than the adjacent value.
In order to address these errors within flash cells, it is known to provide error correction mechanisms within the read path. FIG. 3 of the accompanying drawings illustrates such an arrangement. In the system of FIG. 3 an integrated circuit flash memory 14 is coupled to a processor 16. The processor 16 can store data values into the flash memory 14 and read data values from the flash memory 14. The flash memory 14 contains an array 18 of flash memory cells 20. This array 18 includes a portion 22 storing the data values written by the processor 16 as well as the portion 24 storing error correction codes. The error correction code (ECC) codewords are written by error correcting circuitry 26 disposed in the data path between the processor 16 and the array 18. The error correction code is typically a systematic code where the codewords are the original data, with parity data added into the stored data when it is written and are used when the stored data is read so as to detect any errors within that stored data and correct any detected errors if they are within the capability for correction by the error correcting codes (e.g. the errors are not too extensive). Such mechanisms are able to reduce the statistical likelihood of a read error as would be observed by the data sink in processor 16, interfacing with the ECC protected NAND 14, to acceptable levels, even though many individual flash cells may be defective.
A problem with the system of FIG. 3 is that the storage requirement for the error correcting codes within the portion 24 represents a disadvantageous storage overhead which reduces the overall capacity of the array 18 for storing useful data. Measures which can reduce the amount of error correcting codes which need to be stored in order to provide appropriate error correction are advantageous as they will release storage capacity within the array 18 for use in storing the working data to be written and read by the processor 16. Another problem with the system of FIG. 3 is that the error correction mechanism 26 introduces a disadvantageous latency into the reading and writing operations from the array 16 which reduces the system performance. Furthermore, the error correction mechanism 16 can be relatively large and complex thereby disadvantageously increasing the size, cost and access speed of the system. It will be appreciated that measures which can reduce the overhead associated with the error correction requirements of the flash memory cells whilst maintaining data integrity are advantageous.